1. Technical Field
The disclosure relates in general to a display, and more particularly to a display capable of independently generating start signals and output signals respectively.
2. Description of the Related Art
Referring to FIG. 1 and FIG. 2. FIG. 1 shows a conventional shift register circuit. FIG. 2 shows a signal timing diagram of FIG. 1. The conventional shift register circuit 122 comprises a plurality of stages of shift registers. For convenience of elaboration, the shift registers are exemplified by a first stage shift register SR1 to a fourth stage shift register SR4. The first stage shift register SR1 to the fourth stage shift register SR4 generate a first stage output signal O1 to a fourth stage output signal O4. The first stage output signal O1 generated by the first stage shift register SR1 is inputted to start the second stage shift register SR2 to generate a second stage output signal O2. The second stage output signal O2 generated by the second stage shift register SR2 is inputted to start the third stage shift register SR3 to generate a third stage output signal O3. The third stage output signal O3 generated by the third stage shift register SR3 is inputted to start the fourth stage shift register SR4 to generate a fourth stage output signal O4. The operation of the output signals of other stages can be obtained in the same manner.
Referring to FIG. 3, a circuit diagram of a first conventional shift register is shown. The first stage shift register SR1 comprises transistors T1˜T4. The transistor T1 outputs a first stage output signal O1 according to a clock signal CK1. The transistor T2 is coupled to the transistor T1 and controlled by the second stage output signal O2 outputted from the second stage shift register SR. The transistor T3 is controlled by the second stage output signal O2 outputted from the second stage buffer shift register SR2. The transistor T4 is coupled to the transistor T3 for driving the transistor T1 according to the first stage start signal STV. The transistor T2 is coupled to the transistor T1 and a coupling capacitor Cb. The circuit design of the second stage shift register SR2 is similar to that of the first stage carry shift register SR1, and the similarities are not repeated here.
Referring to FIG. 4, a circuit diagram of a second conventional shift register is shown. FIG. 4 is different from of FIG. 3 in that the shift registers SR1′ and SR2′ of FIG. 4 further comprise a transistor T5. The transistor T5 is controlled by the potential of a node B to selectively output a start signal C2 to start the shift register SR2 according to the clock signal CK1.
In the display region (also referred as active matrix array region) of the display panel, the scan lines and the data lines are interlaced, when the voltage on the data lines varies, the voltage on the scan lines varies as well. Thus, the output signal of the conventional shift register circuit will be interfered with by the noises. When the output signal interfered with by the noises is inputted to the next stage shift register, the noises will be amplified and cause abnormal operation to the shift register circuit.